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售價:284  |
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詳細資料ISBN：9789866116438 叢書系列：理工叢書 規格：平裝 / 200頁 / 17 X 23 X 1 CM / 普通級 / 單色印刷 / 初版 出版地：台灣 內容簡介 射頻積體電路 (RFIC) 晶片主要可分為功率放大器 (POWER AMPLIFIER)、收發器 (TRANSCEIVER)、鎖相迴路 (PHASE LOCK LOOP) 三大部分。目前鎖相迴路與收發器已逐漸整合於系統晶片 (SOC)，剩下的功率放大器成為最後等待整合的聖杯 (HOLY GRAIL)。功率放大器大量使用於手機、WI-FI無線區域網路、平板電腦、藍芽等網通產品，如GSM手機使用1顆，GPRS使用2顆，3G使用4顆、3.5G使用6顆，而WLAN 802.11A、802.11A+G使用1～2顆， 802.11N則增至4～6 顆。隨著手持無線通信裝置滲透率提升，功率放大器使用量將大幅提升。 本書的目的係提供一功率放大器的設計平台，以幫助設計者透過簡單操作步驟，循序漸進地完成設計流程，如分析最佳匹配阻抗、最大輸出功率傳遞、穩定度、匹配網路、大訊號分析、功率增進效率等重要功率放大器設計參數。最後以四個功率放大器實例設計完成驗證。 POWER AMPLIFIER (PA) IS THE MOST IMPORTANT CIRCUIT IN TRANSMITTER IN MOBILE COMMUNICATION SYSTEMS, WHICH IS USED TO CONVERT A DC POWER INTO A RADIO-FREQUENCY (RF) SIGNAL OF SIGNIFICANT POWER TO DRIVE THE ANTENNA OF THE TRANSMITTER. THE PA ENTAILS THE ISSUES OF THE OUTPUT POWER AT OUTPUT 1-DB GAIN COMPRESSION POINT (OP1DB), SATURATED OUTPUT POWER (PSAT), POWER ADDED EFFICIENCY (PAE), OUTPUT THIRD-ORDER INTERMODULATION INTERCEPT POINTS (OIP3), INPUT/OUTPUT RETURN LOSSES, AND POWER GAIN. THE OBJECTIVE OF THIS BOOK IS TO INTRODUCE THE DESIGN FLOW, SPECIFICATIONS AND CIRCUIT DESIGN PROCEDURE OF THE COMMONLY USED PAS. THE DESIGN PROCEDURE DIVIDES INTO TWO PARTS: DEVICE CHARACTERISTICS AND CIRCUIT SIMULATIONS. EACH PA CIRCUIT IS SIMULATED BY THE AGILENT ADVANCED DESIGN SYSTEMTM (ADS) SIMULATOR WHICH DESIGN GUIDE FOR PA DESIGN HAS BEEN ALREADY BUILT. THIS BOOK IS USED IN 3 TO 4-WEEK LAB COURSE INCORPORATED WITH ADS DESIGN AND PA IMPLEMENTATION. THE BOOK PROVIDES A STEP-BY-STEP DESIGN PROCEDURE FOR THE PA DESIGN. THE DESIGN FLOW DESCRIBES THE PROCESSES OF CIRCUIT DESIGN. FIRST, WE WILL SPECIFY THE SPECIFICATIONS AND MAKE THE DESIGNED PA TO CONFORM THE SPECIFICATIONS. MEANWHILE, WE WILL SELECT THE PROPER DEVICE AND BIAS CONDITIONS TO MEET THE AFOREMENTIONED REQUIREMENT. IN THE BEGINNING OF CIRCUIT DESIGN, WE WILL CHECK THE DC, AC AND LOAD-PULL ANALYSES OF THE DEVICE BY USING AGILENT ADS SIMULATOR. IN THE DC ANALYSIS, WE WILL SHOW THE I-V CURVE TO DETERMINE THE BIAS POINT AND CLASSES OF THE PA. IN THE LOAD-PULL ANALYSIS, WE WILL USE ONE-TONE LOAD-PULL SIMULATION TO CALCULATE THE MAXIMUM OUTPUT POWER AND LOAD IMPEDANCE. THE SIMULATOR ALSO SHOWS S-PARAMETERS, STABILITY, AND GP CIRCLES IN THE SMALL SIGNAL ANALYSIS. THEN, WE WILL CHOOSE AND MATCHING NETWORKS ACCORDING TO FREQUENCY, BANDWIDTH, AND GAIN, ETC. THE PA SHOULD MATCH THE OUTPUT AND INPUT IMPEDANCES TO ACHIEVE THE MAXIMUM OUTPUT POWER AND PAE. SUBSEQUENTLY, THE ONE-TONE AND TWO-TONE SIMULATIONS ARE PERFORMED. IN THE LARGE SIGNAL ANALYSIS, WE WILL PERFORM ONE-TONE AND TWO-TONE SIMULATIONS WHICH ESTIMATE OP1DB, PSAT, PAE, AND OIP3. WE WILL FIND THE OPTIMUM PERFORMANCE FOR THE REQUIREMENTS OF THE SPECIFICATIONS BY CAREFUL ADJUSTMENT OF DEVICE SELECTION, BIAS CONDITIONS AND MATCHING NETWORKS. THUS, THE CIRCUIT DESIGN CAN BE COMPLETED. THE ORGANIZATION OF THIS BOOK TEXT IS AS FOLLOWS: CHAPTER 1 PRESENTS A GENERAL THE SPECIFICATIONS AND DESIGN FLOW OF PA. CHAPTER 2 PRESENTS CATEGORIES OF PA OPERATION AND S-PARAMETER REPRESENTATION. CHAPTER 3 GIVES THE STABILITY ANALYSIS. CHAPTER 4 INTRODUCES CRIPPS LOADLINE METHOD. CHAPTER 5 PRESENTS THE GAIN AND POWER MATCHING, RESPECTIVELY. CHAPTER 6 INTRODUCES LARGE SIGNAL ANALYSIS. CHAPTERS 7 TO 10 GIVE THE DESIGN EXAMPLES OF SINGLE AND TWO-STAGE CLASS AB, PUSH-PULL CLASS B AND CLASS E PA DESIGNS. |
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